LAB CODE: VLS-TR-01
LSI Development Board with Wireless Communication - On board 2.4GHz wireless trans-receiver.
LAB CODE: VLS-TR-02
VLSI Development Platform - FPGA (XILINX Spartan2) Application Development Board (50K Gates, 1728 logic cells), I/O ports 176, Number of pins 208. The I/O experiments board. Webpack 4.2 Development Software CD.
LAB CODE: VLS-TR-03
FPGA Development Platform - XILINX Spartan3,FPGA ,400K Gates,8064 logic cells). I/O ports 136, Number of pins 208
LAB CODE: VLS-TR-04
CPLD Development Platform [XC95108 PC84] - CPLD (Xilinx XC95108PC84) Development Board. 108 macrocells with 2400 usable gates, 84 users I/O pins.
LAB CODE: VLS-TR-05
Wireless Sensor Network Training System - 2.4GHz Wireless Transreceiver. FPGA. DIP switches for Logic Inputs.
LAB CODE: VLS-TR-06
Universal Development Platform - Xilinx FPGA Daughter Card. Xilinx CPLD Daughter Card. Xilinx Virtex 2 FGPA Daughter Card (Optional).
LAB CODE: VLS-TR-07
Video Processing Platform - Xilinx FPGA for implementing Video Processing Algorithms. Multi format SDTV Video Decoder with composite,YPrPb and S-video Input.
LAB CODE: VLS-TR-09
Virtex-4 Development Platform - Virtex-4 Development Platform is an ideal solution for higher end FPGA applications. It comes with a XC4VLX25-10FF668C device on board which has a capacity of ~25K logic cells or~1.4million system gates.
LAB CODE: VLS-TR-10
Digital Communication Training System is an ideal solution to bridge the gap between theoretical studies and practical working. Using this training system student will be able to understand step by step journey of communication system.
All major blocks required in Digital Communication blocks are covered and test points are provided for each step.
Inbuilt Mixed Signal Oscilloscope-MSO [CH1+ ...
LAB CODE: VLS-TR-11
CDMA-Direct Sequence Spread Spectrum (DSSS) Trainer provides a basic understanding of the concepts behind CDMA, and various issues that need to be considered in the design of a DSSS system. This includes generation of various pseudorandom (PN) codes like Gold, MLS & Barker with programmable tappings, variable chip rate, and digital modulations BPSK, QPSK & digital AWGN noise with ...
LAB CODE: VLS-TR-12
VLSI Embedded System Trainers - XPO series: Aesthetically designed Injection molded Plastic enclosure XPO series of Embedded trainers VIZ; CPLD, FPGA, 89C51Rd2, PIC, 68HC11 etc Supports use of 5V tolerant ICs (FPGA etc.)
LAB CODE: VLS-TR-13
Embedded Software Design Platform XPO Series - Aesthetically designed injection moulded enclosure. Intel 200MHz PXA255 RISC processor with 32MB Flash Memory and 64MB SDRAM. Xscale architecture suitable for mobile computing technology (HDD) and facilitates Kernel space programming as compared to user space programming available on competing mode User’s/Student’s (Application ...